1. Field of the Invention
The present invention relates to an apparatus and a method for verifying a designed semiconductor integrated circuit, particularly to an verifying apparatus for automatically determining whether changes of voltages and currents meet predetermined conditions for the designed circuit.
2. Description of the Related Art
As a semiconductor integrated circuit (LSI) has been recently increased in size and integration degree, various apparatuses are developed to support circuit design and verification.
For example, FIG. 14 shows an automatic circuit designing apparatus for designing and verifying a semiconductor integrated circuit. For the apparatus shown in FIG. 14, a designer uses a plurality of prepared basic cells 251 for defining a predetermined circuit pattern as parts and supplies a generator 201 with the parts and a generation parameter 250 corresponding to a specification of a design circuit. The generator 201 generates a circuit schematic (circuit diagram) 252 of the whole circuit in accordance with the supplied generation parameter 250 by tiling with the basic cells.
Then, the designer generates a verification pattern 254 while referring to the circuit schematic thus generated and confirming the name of a signal to be verified. A circuit simulation is executed by a circuit simulator 202 by using the verification pattern 254 to generate a simulation result 255. Then, the designer visually confirms the result and determines whether each circuit meets a desired specification.
As described above, a verification pattern used for a circuit simulation is manually generated by a designer. To execute the circuit simulation, the name of a signal to be verified is necessary. However, the signal name cannot be known before the circuit schematic 252 is generated by the generator 201. Therefore, it is necessary for the designer to generate the verification pattern 254 for the circuit simulator 202 after generating the circuit schematic 252 and then, referring to the circuit schematic 252 to examine the signal name. Therefore, when a circuit pattern to be designed is different, the designer must generate the verification pattern 254 every circuit pattern and the work load increases.
Moreover, because acceptance or rejection of the simulation result 255 is manually determined by a designer, there is a problem that an error occurs or the designer is burdened.
As a semiconductor integrated circuit has been recently increased in size and integration degree, the circuit has been further complicated and sophisticated and it is estimated that the load of the designer under operations is further increased in future. Therefore, it is requested to automate the operations.
The present invention is made to solve the above problems and its object is to provide an apparatus for automatically verifying a designed circuit in automatic circuit designing of a semiconductor integrated circuit.
In a first aspect of the invention, an apparatus is provided for automatically verifying a circuit which is generated by a generator for generating a circuit diagram of a whole semiconductor integrated circuit in accordance with an arrangement of cells which are regarded as parts. Each cell defines a predetermined circuit unit.
A verification symbol which specifies a node name and a verification content for a node to be verified is inserted in advance into at least one of the cells arranged as parts. The apparatus comprises verification-condition extracting section, pattern generating section and acceptance/rejection determining section.
The verification-condition extracting section analyzes a circuit diagram of the whole semiconductor integrated circuit generated in accordance with the arrangement of cells including at least one verification symbol, and extracts the node name and the verification content of the node to be verified. The pattern generating section generates a verification pattern to be used for verification from the extracted node name and verification content. The acceptance/rejection determining section executes a circuit simulation by using the verification pattern, analyzes the simulation result, and determines whether the verified node is of acceptance or rejection.
Thus, the circuit verification can be done automatically, the work load of a designer can be reduced, and an error in the work of the designer can be prevented.
In the apparatus, the acceptance/rejection determining section may output a report including a determination result indicative of acceptance or rejection. Thus it becomes easier to perceive a determination result.
The apparatus further may comprise display section for highlighting rejected portions in the whole circuit in accordance with a determination result from the acceptance/rejection determining section for display. Thereby, rejected portions are easily recognized.
In the apparatus, in order to verify a skew between two signals connected to two nodes included in the same cell, the verification symbol may have a first connection terminal to be connected to one of the signals and a second connection terminal to be connected to the other of the signals. Thereby, verification between two signals is realized.
In the apparatus, in order to verify a signal to be connected to two nodes included in different cells, the verification symbol may have a first connection terminal to be connected to a signal to be measured in a cell into which the verification symbol is inserted and a second connection terminal for specifying a signal to be measured in another cell into which the verification symbol is not inserted. In this case, a virtual symbol name to specify a signal to be connected can be defined on the second connection terminal. Thereby, it is possible to verify signals to be connected to two nodes included in different cells.
In the apparatus, the verification symbol may have a connection terminal for designating predetermined waveform data to be compared with a signal to be measured. Thus it becomes possible to compare with any waveform data which have already been obtained.
In the apparatus, the verification symbol may have a connection terminal to be connected to a predetermined signal which is used as a signal providing a reference potential. Thereby, it is possible to use any one of signals as the reference potential.
In the apparatus, the verification symbol may measure a period in which voltage difference between two signals to be compared in verification becomes a predetermined value or more, and determine acceptance or rejection in accordance with whether the length of period is equal to or shorter than a predetermined length. Thus, secure determination can be realized.
In the apparatus, the verification symbol may have a terminal to be connected to an instance in order to verify a current flowing through the instance. Thus, it becomes possible to verify the instance.
In a second aspect of the invention, an apparatus is provided for automatically verifying a semiconductor integrated circuit specified in accordance with circuit information. At least one verification symbol which specifies a node name and a verification content for a node to be verified in the circuit is inserted in advance into the circuit information of the semiconductor integrated circuit. The apparatus comprises verification-condition extracting section, pattern generating section, and acceptance/rejection determining section.
The verification-condition extracting section analyzes a circuit information including the verification symbol, and extracts the node name and verification content of the node to be verified.
The pattern generating section generates a verification pattern to be used for verification from the extracted node name and verification content.
The acceptance/rejection determining section executes a circuit simulation by using the verification pattern, analyzes the simulation result, and determines whether the verified node is of acceptance or rejection.
Thus, the circuit verification can be done automatically, the work load of a designer can be reduced, and an error in the work of the designer can be prevented.
In a third aspect of the invention, provided is a method of automatically verifying a designed circuit which is generated by a generator for generating a circuit diagram of a whole semiconductor integrated circuit in accordance with an arrangement of cells which are regarded as parts, each cell defining a predetermined circuit unit. A verification symbol which specifies a node name and a verification content for a node to be verified is inserted in advance into at least one of the cells arranged as parts. The method comprises analyzing a circuit diagram of the whole semiconductor integrated circuit generated in accordance with the arrangement of cells including at least one verification symbol, and extracting the node name and the verification content of the node to be verified, generating a verification pattern to be used for verification from the extracted node name and verification content, and executing a circuit simulation by using the verification pattern and then analyzing the simulation result to determine whether the verified node is of acceptance or rejection.
In a fourth aspect of the invention, provided is a method of automatically verifying a designed semiconductor integrated circuit specified in accordance with circuit information. At least one verification symbol which specifies a node name and a verification content for a node to be verified in the circuit is inserted in advance into the circuit information of the semiconductor integrated circuit. The method comprises analyzing a circuit information including the verification symbol, and extracting the node name and verification content of the node to be verified, generating a verification pattern to be used for verification from the extracted node name and verification content, and executing a circuit simulation by using the verification pattern and then analyzing the simulation result to determine whether the verified node is of acceptance or rejection.